1. Field of Invention
The present invention relates to a shift frequency demultiplier, and more particularly to a shift frequency demultiplier with the automatic reset function.
2. Description of Related Arts
The shift frequency demultiplier and the count frequency demultiplier are two kinds of common frequency demultipliers.
Compared with the shift frequency demultiplier, the count frequency demultiplier has more complex control logic and can not meet the timing requirements in the high frequency design, thus it is commonly used to design the frequency demultiplier with middle and low frequency clocks. The shift frequency demultiplier has much easier control logic and can meet the timing requirements in the high frequency design, thus it is commonly used to design the frequency demultiplier with high frequency clock. However, the shift frequency demultiplier has a fatal defect that the quality of the frequency-demultiplied clock entirely depends on the initial state of the register group and the state transition during the operation. Once the error of the state occurs due to some unexpected reasons, the error of the frequency demultiplication, even the entire error will be directly produced.
FIG. 1 is a circuit diagram of an existing five-frequency demultiplication shift frequency demultiplier which comprises five registers connected with each other. The reset end Sn or Rn of every register is connected with an input reset signal RSTn, the clock end CK of every register is connected with an input clock signal CLK. Every register has an input end D and an output end Q. FIG. 2 is a waveform graph of FIG. 1. When the output end Q of the fifth register outputs a high level signal, the clock signal CLKo is high level, thereby frequency-demultiplying the input clock signal CLKi. Referring to FIG. 3, if the state of the shift frequency demultiplier is changed to be “0000” due to the reason that the error occurs at the intermediate state, the shift frequency demultiplier can't be normally recovered, thus the error of the shift frequency demultiplication occurs. Referring to FIG. 4, if the state of the shift frequency demultiplier is changed to be “1111” due to the reason that the error occurs at the intermediate state, the shift frequency demultiplier can't be normally recovered, thus the error of the shift frequency demultiplication occurs. Referring to FIG. 5, if discontinuous “0” or “1” occurs due to the reason that the error occurs at the intermediate state, the shift frequency demultiplier can't be normally recovered, thus the error of the shift frequency demultiplication occurs.